module top (
    input wire clk,
    input wire rst,
    input wire [31:0] data_in_data [0:15],
    input wire [15:0] data_in_vld,
    output wire [15:0] sop,
    output wire [15:0] eop,
    output wire [15:0] vld,
    output wire [31:0] port_data_out [0:15]
);
    reg [9:0] dataSeed [0:15];
    //端口输出的写数据�??要用到的信号
    wire [15:0] write_en_port_group;
    wire [9:0] write_size_port_group [0:15];
    wire [5:0] write_priority_port_group [0:15];
    wire [15:0] write_target_port_group [0:15];
    wire [9:0] write_size_port_special [0:15];
    wire [5:0] write_priority_port_special [0:15];
    wire [15:0] write_target_port_special [0:15];
    //写仲裁信�??
    wire [15:0] special_arbition;
    wire [15:0] data_ready_in_port;
    wire [31:0] data_in_port [0:15];

    //输入到RAM的控制信�??
    wire [15:0] write_en_sram;
    wire [9:0] write_size_sram [0:15];
    wire [5:0] write_priority_sram [0:15];
    wire [15:0] write_port_sram [0:15];
    wire [15:0] port_pick_sram;
    wire [15:0] data_ready_out_special;
    wire [31:0] data_out_special [0:15];
    wire [3:0] data_ready_in_port_common [0:3];
    wire [31:0] data_in_port_common_group1 [0:3];
    wire [31:0] data_in_port_common_group2 [0:3];
    wire [31:0] data_in_port_common_group3 [0:3];
    wire [31:0] data_in_port_common_group4 [0:3];
    wire [3:0] data_ready_out_port_common [0:3];
    wire [31:0] data_out_port_common_group1 [0:3];
    wire [31:0] data_out_port_common_group2 [0:3];
    wire [31:0] data_out_port_common_group3 [0:3];
    wire [31:0] data_out_port_common_group4 [0:3];
    //空间管理器输出的内容
    wire [15:0] address_ready_special;
    wire [15:0] address_ready_common;
    //空间管理器输出的入队信号
    wire [15:0] enqueue_en_in;
    wire [5:0] enqueue_priority_in [0:15];
    wire [9:0] enqueue_value_in [0:15];
    wire [15:0] enqueue_port_in [0:15];
    reg [15:0] enqueue_en_out;
    reg [5:0] enqueue_priority_out [0:15];
    reg [15:0] enqueue_value_out [0:15];
    wire [15:0] enqueue_en_special_in;
    wire [5:0] enqueue_priority_special_in [0:15];
    wire [9:0] enqueue_value_special_in [0:15];
    wire [15:0] enqueue_en_special_out;
    wire [5:0] enqueue_priority_special_out [0:15];
    wire [15:0] enqueue_value_special_out [0:15];
    wire [15:0] enqueue_port_special_in [0:15]; 
    wire [15:0] enqueue_success;
    wire [31:0] dequeue_success;
    wire hand_ack;
    //目录模块输出的信�?
    wire [15:0] dequeue_vld_dict;
    wire [5:0] dequeue_priority_dict [0:15];
    wire [15:0] dequeue_value_dict [0:15];
    wire [15:0] dequeue_vld_cram;
    wire [9:0] dequeue_value_cram [0:15];
    wire [15:0] dequeue_vld_sram;
    wire [9:0] dequeue_value_sram [0:15];
    //组管理器输出的信�?
    wire [3:0] write_en_cram;
    wire [9:0] write_size_cram [0:3];
    wire [5:0] write_priority_cram [0:3];
    wire [15:0] write_port_cram [0:3];
    wire [3:0] ram_pick [0:3];
    wire [3:0] write_arbition [0:3];

    //空间管理器输出的信号
    wire [15:0] manager_write_ready_group;
    wire [15:0] manager_write_ready_special;
    wire [15:0] manager_read_ready_group;
    wire [15:0] manager_read_ready_special;
    //输出端口使用的信�?
    wire [15:0] date_en_output_in_special;
    wire [31:0] data_output_in_special [0:15];
    wire [15:0] date_en_output_in_common;
    wire [31:0] data_output_in_common [0:15];
    wire [15:0] channal_en;
    wire [5:0] channal_from [0:15];
    wire [15:0] date_en_output_in;
    wire [15:0] data_en_port_common;
    wire [31:0] data_port_common [0:15];
    wire [15:0] data_en_port_special;
    wire [31:0] data_port_special [0:15];
    wire [31:0] data_output_in [0:15];
    wire [15:0] port_idle_state;
    wire [15:0] transmission_over_sram, transmission_over_cram;
    wire [15:0] enqueue_ack_sram, enqueue_ack_cram;
    wire [15:0] transmission_sram [0:15];
    wire [15:0] transmission_cram [0:15];

    //输出文件创建单元的信�?
    wire [31:0] file_out_data [0:15];

    


    initial begin
        dataSeed[0] = 281;
        dataSeed[1] = 271;
        dataSeed[2] = 289;
        dataSeed[3] = 274;
        dataSeed[4] = 290;
        dataSeed[5] = 291;
        dataSeed[6] = 265;
        dataSeed[7] = 266;
        dataSeed[8] = 268;
        dataSeed[9] = 269;
        dataSeed[10] = 292;
        dataSeed[11] = 211;
        dataSeed[12] = 241;
        dataSeed[13] = 257;
        dataSeed[14] = 267;
        dataSeed[15] = 264;
    end

    //数据发生�??
    genvar g1, g2, g3, g4;
    generate
        for (g1=0; g1<4; g1=g1+1) begin : genGroup1
            portIn in(.clk(clk), .rst(rst), .vld(data_in_vld[g1]), .data_in(data_in_data[g1]), .special_arbition(special_arbition[g1]), .special_idle(manager_write_ready_special), .common_arbition(write_arbition[0][g1]), .sram_write_en(write_en_sram),
                            .group_memory_pick(ram_pick[0]), .group_address_ready(address_ready_common[3:0]), .address_ready(address_ready_special), .data_ready(data_ready_in_port[g1]), .data(data_in_port[g1]), 
                            .data_priority(write_priority_port_special[g1]), .data_target_port(write_target_port_special[g1]), .data_size(write_size_port_special[g1]), 
                            .group_priority(write_priority_port_group[g1]), .group_target_port(write_target_port_group[g1]), .group_write_en(write_en_port_group[g1]), .group_size(write_size_port_group[g1]), .group_data_ready(data_ready_in_port_common[0][g1]), .group_data(data_in_port_common_group1[g1]));
        end
    endgenerate

    generate
        for (g2=0; g2<4; g2=g2+1) begin : genGroup2
            portIn in(.clk(clk), .rst(rst), .vld(data_in_vld[g2+4]), .data_in(data_in_data[g2+4]), .special_arbition(special_arbition[g2+4]), .special_idle(manager_write_ready_special), .common_arbition(write_arbition[1][g2]), .sram_write_en(write_en_sram),
                            .group_memory_pick(ram_pick[1]), .group_address_ready(address_ready_common[7:4]), .address_ready(address_ready_special), .data_ready(data_ready_in_port[g2+4]), .data(data_in_port[g2+4]), 
                            .data_priority(write_priority_port_special[g2+4]), .data_target_port(write_target_port_special[g2+4]), .data_size(write_size_port_special[g2+4]), 
                            .group_priority(write_priority_port_group[g2+4]), .group_target_port(write_target_port_group[g2+4]), .group_write_en(write_en_port_group[g2+4]), .group_size(write_size_port_group[g2+4]), .group_data_ready(data_ready_in_port_common[1][g2]), .group_data(data_in_port_common_group2[g2]));
        end
    endgenerate

    generate
        for (g3=0; g3<4; g3=g3+1) begin : genGroup3
            portIn in(.clk(clk), .rst(rst), .vld(data_in_vld[g3+8]), .data_in(data_in_data[g3+8]), .special_arbition(special_arbition[g3+8]), .special_idle(manager_write_ready_special), .common_arbition(write_arbition[2][g3]), .sram_write_en(write_en_sram),
                            .group_memory_pick(ram_pick[2]), .group_address_ready(address_ready_common[11:8]), .address_ready(address_ready_special), .data_ready(data_ready_in_port[g3+8]), .data(data_in_port[g3+8]), 
                            .data_priority(write_priority_port_special[g3+8]), .data_target_port(write_target_port_special[g3+8]), .data_size(write_size_port_special[g3+8]), 
                            .group_priority(write_priority_port_group[g3+8]), .group_target_port(write_target_port_group[g3+8]), .group_write_en(write_en_port_group[g3+8]), .group_size(write_size_port_group[g3+8]), .group_data_ready(data_ready_in_port_common[2][g3]), .group_data(data_in_port_common_group3[g3]));
        end
    endgenerate

    generate
        for (g4=0; g4<4; g4=g4+1) begin : genGroup4
            portIn in(.clk(clk), .rst(rst), .vld(data_in_vld[g4+12]), .data_in(data_in_data[g4+12]), .special_arbition(special_arbition[g4+12]), .special_idle(manager_write_ready_special), .common_arbition(write_arbition[3][g4]), .sram_write_en(write_en_sram),
                            .group_memory_pick(ram_pick[3]), .group_address_ready(address_ready_common[15:12]), .address_ready(address_ready_special), .data_ready(data_ready_in_port[g4+12]), .data(data_in_port[g4+12]), 
                            .data_priority(write_priority_port_special[g4+12]), .data_target_port(write_target_port_special[g4+12]), .data_size(write_size_port_special[g4+12]), 
                            .group_priority(write_priority_port_group[g4+12]), .group_target_port(write_target_port_group[g4+12]), .group_write_en(write_en_port_group[g4+12]), .group_size(write_size_port_group[g4+12]), .group_data_ready(data_ready_in_port_common[3][g4]), .group_data(data_in_port_common_group4[g4]));
        end
    endgenerate

    

    //专用RAM仲裁请求交换网络
    port2RamDataInCrossBar dataInCrossBar(.clk(clk), .rst(rst), .data_ready_in(data_ready_in_port), .data_in(data_in_port),
                                        .data_priority_in(write_priority_port_special), .data_size_in(write_size_port_special), .data_target_port_in(write_target_port_special), 
                                        .write_en_out(write_en_sram), .data_priority_out(write_priority_sram), .data_size_out(write_size_sram), .data_target_port_out(write_port_sram), .port_pick(special_arbition), .data_ready_out(data_ready_out_special), .data_out(data_out_special));
   
    /*
     * 空间管理单元
     * 0-15 专用型RAM，只存储对应目标端口的数据包
     * 16-31 通用型RAM，可以存储任意数据包
    */
    genvar mmuIndex1;
    generate
        for (mmuIndex1=0; mmuIndex1<16; mmuIndex1=mmuIndex1+1) begin : SpecialMemoryManagerUnit
            specialMemoryManager mmu(.clk(clk), .rst(rst), 
                                    .ram_pick(), .write_en(write_en_sram[mmuIndex1]), .write_size(write_size_sram[mmuIndex1]), .write_priority(write_priority_sram[mmuIndex1]), .write_port(write_port_sram[mmuIndex1]), 
                                    .data_en_in(data_ready_out_special[mmuIndex1]), .data_in(data_out_special[mmuIndex1]), 
                                    .dequeue_en(dequeue_vld_sram[mmuIndex1]), .dequeue_value(dequeue_value_sram[mmuIndex1]), .enqueue_sucess(transmission_over_sram), .enqueue_ack(enqueue_ack_sram[mmuIndex1]),
                                    .enqueue_en_out(enqueue_en_special_in[mmuIndex1]), .enqueue_priority_out(enqueue_priority_special_in[mmuIndex1]), .enqueue_value_out(enqueue_value_special_in[mmuIndex1]), .enqueue_port_out(enqueue_port_special_in[mmuIndex1]), .dequeue_success(dequeue_success[mmuIndex1]),
                                    .manager_read_ready(manager_read_ready_special[mmuIndex1]), .manager_write_ready(manager_write_ready_special[mmuIndex1]), .address_ready(address_ready_special[mmuIndex1]), .data_en_out(data_en_port_special[mmuIndex1]), .data_out(data_port_special[mmuIndex1]));
        end
    endgenerate

    //专用RAM的入队增强单元，将入队信号拓展到16�?
    enqueueMuxerSpecial muxSpecial(.clk(clk), .rst(rst), .enqueue_sucess(transmission_over_sram), .enqueue_ack(enqueue_ack_sram),
                                .enqueue_en_in(enqueue_en_special_in), .enqueue_priority_in(enqueue_priority_special_in), .enqueue_value_in(enqueue_value_special_in), 
                                .enqueue_en_out(enqueue_en_special_out), .enqueue_priority_out(enqueue_priority_special_out), .enqueue_value_out(enqueue_value_special_out));

    //专用RAM的出队增强单元，将出队信号裁剪到10�?
    dequeueSpecialUnit unitSpecial(.clk(clk), .rst(rst), 
                                .dequeue_vld_in(dequeue_vld_dict), .dequeue_value_in(dequeue_value_dict),
                                .dequeue_vld_out(dequeue_vld_sram), .dequeue_value_out(dequeue_value_sram));

    //组管理器
    groupManager manager1(.clk(clk), .rst(rst), .ram_idle_1(manager_write_ready_group[0]), .ram_idle_2(manager_write_ready_group[1]), .ram_idle_3(manager_write_ready_group[2]), .ram_idle_4(manager_write_ready_group[3]), 
                .data_ready_in(data_ready_in_port_common[0]), .data_in(data_in_port_common_group1), .data_ready_out(data_ready_out_port_common[0]), .data_out(data_out_port_common_group1),
                .write_en_1(write_en_port_group[0]), .data_priority_1(write_priority_port_group[0]), .data_size_1(write_size_port_group[0]), .data_target_port_1(write_target_port_group[0]),
                .write_en_2(write_en_port_group[1]), .data_priority_2(write_priority_port_group[1]), .data_size_2(write_size_port_group[1]), .data_target_port_2(write_target_port_group[1]),
                .write_en_3(write_en_port_group[2]), .data_priority_3(write_priority_port_group[2]), .data_size_3(write_size_port_group[2]), .data_target_port_3(write_target_port_group[2]),
                .write_en_4(write_en_port_group[3]), .data_priority_4(write_priority_port_group[3]), .data_size_4(write_size_port_group[3]), .data_target_port_4(write_target_port_group[3]), .write_arbitration(write_arbition[0]), 
                .write_en_out(write_en_cram[0]), .write_priority_out(write_priority_cram[0]), .write_size_out(write_size_cram[0]), .write_port_out(write_port_cram[0]), .pick_ram(ram_pick[0]));

    groupManager manager2(.clk(clk), .rst(rst), .ram_idle_1(manager_write_ready_group[4]), .ram_idle_2(manager_write_ready_group[5]), .ram_idle_3(manager_write_ready_group[6]), .ram_idle_4(manager_write_ready_group[7]), 
                .data_ready_in(data_ready_in_port_common[1]), .data_in(data_in_port_common_group2), .data_ready_out(data_ready_out_port_common[1]), .data_out(data_out_port_common_group2),
                .write_en_1(write_en_port_group[4]), .data_priority_1(write_priority_port_group[4]), .data_size_1(write_size_port_group[4]), .data_target_port_1(write_target_port_group[4]),
                .write_en_2(write_en_port_group[5]), .data_priority_2(write_priority_port_group[5]), .data_size_2(write_size_port_group[5]), .data_target_port_2(write_target_port_group[5]),
                .write_en_3(write_en_port_group[6]), .data_priority_3(write_priority_port_group[6]), .data_size_3(write_size_port_group[6]), .data_target_port_3(write_target_port_group[6]),
                .write_en_4(write_en_port_group[7]), .data_priority_4(write_priority_port_group[7]), .data_size_4(write_size_port_group[7]), .data_target_port_4(write_target_port_group[7]), .write_arbitration(write_arbition[1]), 
                .write_en_out(write_en_cram[1]), .write_priority_out(write_priority_cram[1]), .write_size_out(write_size_cram[1]), .write_port_out(write_port_cram[1]), .pick_ram(ram_pick[1]));

    groupManager manager3(.clk(clk), .rst(rst), .ram_idle_1(manager_write_ready_group[8]), .ram_idle_2(manager_write_ready_group[9]), .ram_idle_3(manager_write_ready_group[10]), .ram_idle_4(manager_write_ready_group[11]), 
                .data_ready_in(data_ready_in_port_common[2]), .data_in(data_in_port_common_group3), .data_ready_out(data_ready_out_port_common[2]), .data_out(data_out_port_common_group3),
                .write_en_1(write_en_port_group[8]), .data_priority_1(write_priority_port_group[8]), .data_size_1(write_size_port_group[8]), .data_target_port_1(write_target_port_group[8]),
                .write_en_2(write_en_port_group[9]), .data_priority_2(write_priority_port_group[9]), .data_size_2(write_size_port_group[9]), .data_target_port_2(write_target_port_group[9]),
                .write_en_3(write_en_port_group[10]), .data_priority_3(write_priority_port_group[10]), .data_size_3(write_size_port_group[10]), .data_target_port_3(write_target_port_group[10]),
                .write_en_4(write_en_port_group[11]), .data_priority_4(write_priority_port_group[11]), .data_size_4(write_size_port_group[11]), .data_target_port_4(write_target_port_group[11]), .write_arbitration(write_arbition[2]), 
                .write_en_out(write_en_cram[2]), .write_priority_out(write_priority_cram[2]), .write_size_out(write_size_cram[2]), .write_port_out(write_port_cram[2]), .pick_ram(ram_pick[2]));

    groupManager manager4(.clk(clk), .rst(rst), .ram_idle_1(manager_write_ready_group[12]), .ram_idle_2(manager_write_ready_group[13]), .ram_idle_3(manager_write_ready_group[14]), .ram_idle_4(manager_write_ready_group[15]), 
                .data_ready_in(data_ready_in_port_common[3]), .data_in(data_in_port_common_group4), .data_ready_out(data_ready_out_port_common[3]), .data_out(data_out_port_common_group4),
                .write_en_1(write_en_port_group[12]), .data_priority_1(write_priority_port_group[12]), .data_size_1(write_size_port_group[12]), .data_target_port_1(write_target_port_group[12]),
                .write_en_2(write_en_port_group[13]), .data_priority_2(write_priority_port_group[13]), .data_size_2(write_size_port_group[13]), .data_target_port_2(write_target_port_group[13]),
                .write_en_3(write_en_port_group[14]), .data_priority_3(write_priority_port_group[14]), .data_size_3(write_size_port_group[14]), .data_target_port_3(write_target_port_group[14]),
                .write_en_4(write_en_port_group[15]), .data_priority_4(write_priority_port_group[15]), .data_size_4(write_size_port_group[15]), .data_target_port_4(write_target_port_group[15]), .write_arbitration(write_arbition[3]), 
                .write_en_out(write_en_cram[3]), .write_priority_out(write_priority_cram[3]), .write_size_out(write_size_cram[3]), .write_port_out(write_port_cram[3]), .pick_ram(ram_pick[3]));


    //空间管理单元
    genvar mmuIndex2;
    generate
        for (mmuIndex2=0; mmuIndex2<4; mmuIndex2=mmuIndex2+1) begin : CommonMemoryManagerUnit1
            memoryManager mmu1(.clk(clk), .rst(rst), 
                            .ram_pick(ram_pick[0][mmuIndex2]), .write_en(write_en_cram[0]), .write_size(write_size_cram[0]), .write_priority(write_priority_cram[0]), .write_port(write_port_cram[0]), 
                            .data_en_in(data_ready_out_port_common[0][mmuIndex2]), .data_in(data_out_port_common_group1[mmuIndex2]), 
                            .dequeue_en(dequeue_vld_cram[mmuIndex2]), .dequeue_value(dequeue_value_cram[mmuIndex2]), .enqueue_sucess(transmission_over_cram), .enqueue_ack(enqueue_ack_cram[mmuIndex2]),
                            .enqueue_en_out(enqueue_en_in[mmuIndex2]), .enqueue_priority_out(enqueue_priority_in[mmuIndex2]), .enqueue_value_out(enqueue_value_in[mmuIndex2]), .enqueue_port_out(enqueue_port_in[mmuIndex2]), .dequeue_success(dequeue_success[mmuIndex2+16]),
                            .manager_read_ready(manager_read_ready_group[mmuIndex2]), .manager_write_ready(manager_write_ready_group[mmuIndex2]), .address_ready(address_ready_common[mmuIndex2]), .data_en_out(date_en_output_in_common[mmuIndex2]), .data_out(data_output_in_common[mmuIndex2]));
        end
    endgenerate

    genvar mmuIndex3;
    generate
        for (mmuIndex3=0; mmuIndex3<4; mmuIndex3=mmuIndex3+1) begin : CommonMemoryManagerUnit2
            memoryManager mmu2(.clk(clk), .rst(rst), 
                            .ram_pick(ram_pick[1][mmuIndex3]), .write_en(write_en_cram[1]), .write_size(write_size_cram[1]), .write_priority(write_priority_cram[1]), .write_port(write_port_cram[1]), 
                            .data_en_in(data_ready_out_port_common[1][mmuIndex3]), .data_in(data_out_port_common_group2[mmuIndex3]), 
                            .dequeue_en(dequeue_vld_cram[mmuIndex3+4]), .dequeue_value(dequeue_value_cram[mmuIndex3+4]), .enqueue_sucess(transmission_over_cram), .enqueue_ack(enqueue_ack_cram[mmuIndex3+4]),
                            .enqueue_en_out(enqueue_en_in[mmuIndex3+4]), .enqueue_priority_out(enqueue_priority_in[mmuIndex3+4]), .enqueue_value_out(enqueue_value_in[mmuIndex3+4]), .enqueue_port_out(enqueue_port_in[mmuIndex3+4]), .dequeue_success(dequeue_success[mmuIndex3+20]),
                            .manager_read_ready(manager_read_ready_group[mmuIndex3+4]), .manager_write_ready(manager_write_ready_group[mmuIndex3+4]), .address_ready(address_ready_common[mmuIndex3+4]), .data_en_out(date_en_output_in_common[mmuIndex3+4]), .data_out(data_output_in_common[mmuIndex3+4]));
        end
    endgenerate

    genvar mmuIndex4;
    generate
        for (mmuIndex4=0; mmuIndex4<4; mmuIndex4=mmuIndex4+1) begin : CommonMemoryManagerUnit3
            memoryManager mmu3(.clk(clk), .rst(rst), 
                            .ram_pick(ram_pick[2][mmuIndex4]), .write_en(write_en_cram[2]), .write_size(write_size_cram[2]), .write_priority(write_priority_cram[2]), .write_port(write_port_cram[2]), 
                            .data_en_in(data_ready_out_port_common[2][mmuIndex4]), .data_in(data_out_port_common_group3[mmuIndex4]), 
                            .dequeue_en(dequeue_vld_cram[mmuIndex4+8]), .dequeue_value(dequeue_value_cram[mmuIndex4+8]), .enqueue_sucess(transmission_over_cram), .enqueue_ack(enqueue_ack_cram[mmuIndex4+8]),
                            .enqueue_en_out(enqueue_en_in[mmuIndex4+8]), .enqueue_priority_out(enqueue_priority_in[mmuIndex4+8]), .enqueue_value_out(enqueue_value_in[mmuIndex4+8]), .enqueue_port_out(enqueue_port_in[mmuIndex4+8]), .dequeue_success(dequeue_success[mmuIndex4+24]),
                            .manager_read_ready(manager_read_ready_group[mmuIndex4+8]), .manager_write_ready(manager_write_ready_group[mmuIndex4+8]), .address_ready(address_ready_common[mmuIndex4+8]), .data_en_out(date_en_output_in_common[mmuIndex4+8]), .data_out(data_output_in_common[mmuIndex4+8]));
        end
    endgenerate

    genvar mmuIndex5;
    generate
        for (mmuIndex5=0; mmuIndex5<4; mmuIndex5=mmuIndex5+1) begin : CommonMemoryManagerUnit4
            memoryManager mmu4(.clk(clk), .rst(rst), 
                            .ram_pick(ram_pick[3][mmuIndex5]), .write_en(write_en_cram[3]), .write_size(write_size_cram[3]), .write_priority(write_priority_cram[3]), .write_port(write_port_cram[3]), 
                            .data_en_in(data_ready_out_port_common[3][mmuIndex5]), .data_in(data_out_port_common_group4[mmuIndex5]), 
                            .dequeue_en(dequeue_vld_cram[mmuIndex5+12]), .dequeue_value(dequeue_value_cram[mmuIndex5+12]), .enqueue_sucess(transmission_over_cram), .enqueue_ack(enqueue_ack_cram[mmuIndex5+12]),
                            .enqueue_en_out(enqueue_en_in[mmuIndex5+12]), .enqueue_priority_out(enqueue_priority_in[mmuIndex5+12]), .enqueue_value_out(enqueue_value_in[mmuIndex5+12]), .enqueue_port_out(enqueue_port_in[mmuIndex5+12]), .dequeue_success(dequeue_success[mmuIndex5+28]),
                             .manager_read_ready(manager_read_ready_group[mmuIndex5+12]), .manager_write_ready(manager_write_ready_group[mmuIndex5+12]), .address_ready(address_ready_common[mmuIndex5+12]), .data_en_out(date_en_output_in_common[mmuIndex5+12]), .data_out(data_output_in_common[mmuIndex5+12]));
        end
    endgenerate

    //目录更新交换网络 -- 入队
    ram2PortEnqueueCrossBar enqueueCrossBar(.clk(clk), .rst(rst), 
                                            .enqueue_en_in(enqueue_en_in), .enqueue_priority_in(enqueue_priority_in), .enqueue_value_in(enqueue_value_in), .enqueue_port_in(enqueue_port_in), .enqueue_sucess(transmission_over_cram), .enqueue_ack(enqueue_ack_cram), 
                                            .enqueue_en_out(enqueue_en_out), .enqueue_priority_out(enqueue_priority_out), .enqueue_value_out(enqueue_value_out));

    //目录更新交换网络 -- 出队
    port2RamDequeueCrossBar dequeueCrossBar(.clk(clk), .rst(rst), 
                                            .dequeue_vld_port(dequeue_vld_dict), .dequeue_priority_port(dequeue_priority_dict), .dequeue_value(dequeue_value_dict), 
                                            .set_channal_en(channal_en), .set_channal_value(channal_from),
                                            .dequeue_vld_ram(dequeue_vld_cram), .dequeue_value_ram(dequeue_value_cram));

    //内容输出交换网络
    ram2PortDataoutCrossBar dataoutCrossBar(.clk(clk), .rst(rst),
                                            .data_en_in(date_en_output_in_common), .data_in(data_output_in_common), .set_en(channal_en), .set_from(channal_from),
                                            .data_en_out(data_en_port_common), .data_out(data_port_common));


    //目录
    genvar oqIndex;
    generate
        for (oqIndex=0; oqIndex<16; oqIndex=oqIndex+1) begin : OutPortQueue
            queueOutSide outQueue(.clk(clk), .rst(rst), 
                                .dict_update_en1(enqueue_en_out[oqIndex]), .dict_update_pri1(enqueue_priority_out[oqIndex]), .dict_update_value1(enqueue_value_out[oqIndex]), 
                                .dict_update_en2(enqueue_en_special_out[oqIndex]), .dict_update_pri2(enqueue_priority_special_out[oqIndex]), .dict_update_value2(enqueue_value_special_out[oqIndex]), .transmission_over1(transmission_over_cram[oqIndex]), .transmission_over2(transmission_over_sram[oqIndex]), .transmission_sram(transmission_sram[oqIndex]), .transmission_cram(transmission_cram[oqIndex]), 
                                .read_ready_sram(manager_read_ready_special), .read_ready_cram(manager_read_ready_group), .port_out_idle(port_idle_state[oqIndex]), .hand_ack(dequeue_success), .dequeue_vld(dequeue_vld_dict[oqIndex]), .dequeue_head_old(dequeue_value_dict[oqIndex]), .old_head_priority(dequeue_priority_dict[oqIndex]));
        end
    endgenerate

    enqueueAckCrossBar ackCrossBar(.enqueue_ack_sram_in(transmission_sram), .enqueue_ack_cram_in(transmission_cram), .enqueue_ack_sram_out(enqueue_ack_sram), .enqueue_ack_cram_out(enqueue_ack_cram));

    //输出端口
    genvar poIndex;
    generate
        for (poIndex=0; poIndex<16; poIndex=poIndex+1) begin :OutPort
            portOut out(.clk(clk), .rst(rst), .dequeue_en_queue(dequeue_vld_dict[poIndex]), .dequeue_value(dequeue_value_dict[poIndex]), 
                        .date_en_group(data_en_port_common[poIndex]), .data_in_group(data_port_common[poIndex]), .data_en_special(data_en_port_special[poIndex]), .data_in_special(data_port_special[poIndex]), 
                        .port_idle(port_idle_state[poIndex]), .sop(sop[poIndex]), .eop(eop[poIndex]), .vld(vld[poIndex]), .port_data_out(port_data_out[poIndex]));
        end
    endgenerate
endmodule